cmos lsi ordering number : en * 5073a o3095ha/63095ha (ot) no. 5073-1/7 preliminary sanyo electric co.,ltd. semiconductor bussiness headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan image sensor signal processing lsi LC99062-W50 overview the LC99062-W50 is an external digital signal processor (dsp) that includes digital ntsc and pal encoders on chip, and that supports color video. the LC99062-W50 is implemented in a single chip using standard cells. package dimensions unit: mm 3151-qfp100e specifications absolute maximum ratings at ta = 25?, v ss = 0 v allowable operating ranges at ta = ?5 to +65?, v ss = 0 v parameter symbol conditions ratings unit maximum supply voltage v dd max ?.3 to +7.0 v i/o voltages v i , v o ?.3 to v dd + 0.3 v allowable power dissipation pd max 850 mw operating temperature topr ?5 to +65 ? storage temperature tstg ?5 to +125 ? soldering conditions hand soldering: 3 seconds 350 ? reflow: 10 seconds 235 ? i/o currents i i , i o per individual i/o reference cell ?0 ma parameter symbol conditions min typ max unit supply voltage v dd 4.75 5.0 5.25 v input voltage range v in 0v dd v [LC99062-W50] sanyo: qip100e
electrical characteristics at ta = ?5 to +65 c, v dd = 4.75 to 5.25 v, v ss = 0 v note: the applicable pin sets are defined as follows: input (1) ...... all input pins except regsel1 and regsel2 (2) ...... regsel1, regsel2 output (3) ...... ot1 to ot24 (4) ...... crkeyh pin assignment no. 5073- 2 /7 LC99062-W50 parameter symbol conditions min typ max unit input high level voltage v ih cmos compatible: applicable pin (1) 0.7 v dd v input low level voltage v il cmos compatible: applicable pin (1) 0.3 v dd v input high level voltage v ih ttl compatible schmitt: applicable pin (2) 2.5 v input low level voltage v il ttl compatible schmitt: applicable pin (2) 0.6 v output high level voltage v oh i oh = ? ma: applicable pin (3) v dd ?2.1 v output low level voltage v ol i ol = 4 ma: applicable pin (3) 0.4 v output high level voltage v oh i oh = ? ma: applicable pin (4) v dd ?2.1 v output low level voltage v ol i ol = 4 ma: applicable pin (4) 0.4 v input leakage current i l v i = v ss , v dd : applicable pins (1) and (2) ?0 +10 a output leakage current i oz in high-impedance output mode: applicable pin (3) ?0 +10 a
pin functions i/o ? i: input pin, o: output pin, b: bidirectional pin, p: power supply pin, nc: unconnected pin no. 5073- 3 /7 LC99062-W50 pin no. symbol i/o function 1 tv i 0: ntsc, 1: pal 2 mirror i 0: normal, 1: mirror 3 v dd p 4 v ss p 5 fsc4 i clk (from lc99052) ntsc: 14.31818 mhz, pal: 14.1875 mhz 6 vd62 i vd (from lc99052) 7 hd62 i hd (from lc99052) 8 aptsw i aperture switch 0: off, 1: on 9 htclk i clk = 8/3fsc (from lc99052) 10 tesdata i 0: run 11 cdsin0 i 8-bit data input (from lc99052) (lsb) 12 cdsin1 i 8-bit data input (from lc99052) 13 cdsin2 i 8-bit data input (from lc99052) 14 cdsin3 i 8-bit data input (from lc99052) 15 cdsin4 i 8-bit data input (from lc99052) 16 cdsin5 i 8-bit data input (from lc99052) 17 cdsin6 i 8-bit data input (from lc99052) 18 cdsin7 i 8-bit data input (from lc99052) (msb) 19 v dd p 20 v ss p 21 ot1 o output channel1 = ch1 (lsb) 22 ot2 o output channel1 = ch1 23 ot3 o output channel1 = ch1 24 ot4 o output channel1 = ch1 25 ot5 o output channel1 = ch1 26 ot6 o output channel1 = ch1 27 ot7 o output channel1 = ch1 28 ot8 o output channel1 = ch1 (msb) 29 ot24 o output channel3 = ch3 (msb) 30 ot23 o output channel3 = ch3 31 ot22 o output channel3 = ch3 32 ot21 o output channel3 = ch3 33 ot20 o output channel3 = ch3 34 ot19 o output channel3 = ch3 35 ot18 o output channel3 = ch3 36 ot17 o output channel3 = ch3 (lsb) 37 ot16 o output channel2 = ch2 (msb) 38 ot15 o output channel2 = ch2 39 ot14 o output channel2 = ch2 40 v ss p 41 v dd p 42 ot13 o output channel2 = ch2 43 ot12 o output channel2 = ch2 44 ot11 o output channel2 = ch2 45 ot10 o output channel2 = ch2 46 ot9 o output channel2 = ch2 (lsb) 47 regsel0 i (regres) 0: register initialization 1: register modification allowed 48 regsel1 i (clks) serial clock input 49 regsel2 i (datas) serial data input 50 regsel3 i 51 regsel4 i regsel [4:0] = (11110) or (11 ** 1); ot (24 to 1) ? high impedance 52 csset1 i must be set according to the phase of the lc99052 a/d converter clock. (this is true for pin 81 as well.) recommended value for current conditions: 1 53 super i superimpose pulse input 1; superimpose 0; camera through 54 ckeyh o chrominance key out h; chrominance key the delay time is changed by the settings of pins 85 and 86. see pins 85 and 86. continued on next page.
continued from preceding page. i/o ? i: input pin, o: output pin, b: bidirectional pin, p: power supply pin, nc: unconnected pin no. 5073- 4 /7 LC99062-W50 pin no. symbol i/o function 55 bin8 i 8-bit data input (msb) 56 bin7 i 8-bit data input 57 bin6 i 8-bit data input 58 bin5 i 8-bit data input 59 bin4 i 8-bit data input 60 bin3 i 8-bit data input or register setting pin 61 bin2 i 8-bit data input or register setting pin 62 bin1 i 8-bit data input (lsb) or register setting pin 63 v dd p 64 gin8 i 8-bit data input (msb) 65 gin7 i 8-bit data input 66 gin6 i 8-bit data input 67 gin5 i 8-bit data input 68 gin4 i 8-bit data input 69 gin3 i 8-bit data input or register setting pin 70 gin2 i 8-bit data input or register setting pin 71 gin1 i 8-bit data input (lsb) or register setting pin 72 v ss p 73 rin8 i 8-bit data input (msb) 74 rin7 i 8-bit data input 75 rin6 i 8-bit data input 76 rin5 i 8-bit data input 77 rin4 i 8-bit data input 78 rin3 i 8-bit data input or register setting pin 79 rin2 i 8-bit data input or register setting pin 80 rin1 i 8-bit data input (lsb) or register setting pin 81 csset2 i must be set according to the phase of the lc99052 a/d converter clock. (this is true for pin 52 as well.) recommended value for current conditions: 1 output mode select 000: video (ot1 to ot8), icon (ot24) 001: r (ot1 to ot8), g (ot9 to ot16), b (ot17 to ot24) 82 omode0 i 010: r-y (ot1 to ot8), y (ot9 to ot16), b-y (ot17 to ot24) 83 omode1 i 011: y (ot1 to ot8), c (ot9 to ot16), csync (ot24) 84 omode2 i 100: y (ot1 to ot8), u/v (ot9 to ot16), uvcont (ot24) 101: vbs (ot1 to ot8), y (ot12 to ot9), r-y (ot16, ot15), b-y (ot14, ot13) 110: vbs (ot1 to ot8), y + csync (ot9 to ot16), c (ot17 to ot24) 111: y/u/v (ot1 to ot8) input mode select 00: r (rin4 to rin8), g (gin4 to gin8), b (bin4 to bin8) * 1 85 imode0 i 01: r (rin4 to rin8), g (gin4 to gin8), b (bin4 to bin8) * 2 86 imode1 i 10: r (rin1 to rin8), g (gin1 to gin8), b (bin1 to bin8) * 1 11: y (rin1 to rin8), v (gin1 to gin8), u (bin1 to bin8) * 1 note: 1. the output is synchronized with the chrominance key out. 2. the chrominance key out is output 16 clock cycles in advance of this output. 87 wbmd1 i white balance mode sw1 88 wbhlh i auto white balance hold; 1: hold, 0: auto note: * hold this pin low when the internal register is used. 89 v dd p 90 v ss p 91 wbmd2 i white balance mode sw2 92 wbmd3 i white balance mode sw3 93 reg1 i register setting pin 94 reg2 i register setting pin 95 reg3 i register setting pin 96 reg4 i register setting pin 97 reg5 i register setting pin 98 reg6 i register setting pin 99 reg7 i register setting pin 100 reg8 i register setting pin
block diagram no. 5073- 5 /7 LC99062-W50
main functions pr o vided b y the LC99062-W50 dsp functions for sanyo color ccd devices (lc9997g/lc9998g) 1. luminance signal system processing includes a luminance matrix to reduce reflected noise (moire). includes a knee-processing circuit using complementary color filters. includes a seven-tap low-pass filter. gamma correction circuit using a five-line approximation technique. the intersection points for each line can be adjusted. provides second-order horizontal outline correction. the gain and coring are adjustable. forms a 1.5 sampling frequency conversion circuit. 2. chrominance system signal processing includes a digital clamping circuit that prevents black balance slippage. forms the rgb signal using an 11-tap low-pass filter and a color calculation matrix. automatic white balance circuit includes all circuits and functions required for automatic white balance. allows switching between automatic and manual modes. allows holding from automatic mode. supports fine-grained gain settings using 7-bit gain data and a technique that takes valid bits into account. the r gain can be set from 0.25 to 4.0, and the b gain from 0.5 to 8.0. provides modes with seven patterns, including flesh correction. reduces incorrect operation by applying a response with hysteresis according to the degree of the discrepancy. gamma correction circuit using a three-line approximation technique includes a linear matrix for color difference signals. allows color tone adjustment. includes a color noise suppression circuit that operates for low chrominance level signals. the suppression level is adjustable. includes a suppression circuit for false color signals that occur at edges and in high-luminance areas. all of the above functions are formed with baseband signals. includes a 1.5x sampling frequency conversion circuit. ntsc/pal encoder ntsc and pal encoding is possible with only hd, vd, and clk inputs (ntsc = 14.31818 mhz, pal = 14.1875 mhz). in pal mode, internal operations are used to generate the fsc signal, and normally there is no need for a fsc signal generated by a pll or other circuit. the csync, cblk, and bf signals are formed internally. allows burst phase adjustment (hue adjustment). (ntsc only) allows pedestal and burst level adjustment. includes a seven-tap low-pass filter for the color difference signals relative to the external rgb inputs. the luminance system 3.58 mhz trap can be turned on or off. input and output modes 1. input modes in addition to signal input from an lc99052-v64a, the LC99062-W50 also supports and input modes. two of the above input systems can be superimposed. 2. output modes the LC99062-W50 supports eight output modes. composite video, 8-bit rgb, , , , and <4-bit y, 2-bit r-y, b-y> and no. 5073- 6 /7 LC99062-W50
ps no. 5073- 7 /7 LC99062-W50 other functions simplified chrominance key function an arbitrary color can be detected by setting r-y and b-y data. a 2-pin serial interface is used for setting registers. stand-alone operation is possible. the adjustments and settings are supported from external pins even in stand- alone mode. support for mirror (left-right reversal) processing. this catalog provides information as of june, 1995. specifications and information herein are subject to change without notice. n no products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n anyone purchasing any products described or contained herein for an above-mentioned use shall: accept full responsibility and indemnify and defend sanyo electric co., ltd., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on sanyo electric co., ltd., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
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